Figure 1 illustrates a previously proposed method utilizing a differential input receiver (Fig. 1a) and the SeMI technique, which employs stub serial termination logic (SSTL) and high-speed transceiver logic (HSTL) interfaces (Fig. 1b). SSTL and HSTL are the single-ended input interface designed for communication with high-speed memory systems, such as double data rate synchronous dynamic random-access memory and are available in available in modern FPGAs. In XILINX's FPGA, the reference voltage (VREF, threshold voltage of input receiver) used for SSTL and HSTL can be supplied externally via VREF pin specifically assigned to IOB (EXTERNAL_VREF) or internally generated in the FPGA fabric (INTERNAL_VREF), which include options like 0.6, 0.675, 0.75, 0.9 V for Xilinx 7 series FPGA. Additionally, there is a limitation that only one VREF value can be used for all input receivers located in the same IOB.

Illustration of the utilization of FPGA input receiver as comparators. a Differential input receivers such as LVDS, b single-ended input receiver such as SSTL/HSTL, and c proposed method

Due to these implementation constraints associated with SSTL/HSTL, Won and Lee's original method presents several practical limitations. Firstly, the FPGA's INTERNAL_VREF typically exceeds 0.6 V, which is too high to effectively trigger SiPMs in TOF PET applications. As a result, the use of EXTERNAL_VREF becomes necessary, requiring the allocation of two additional IO pins per IOB for supplying external reference voltage. Secondly, the inability to apply different threshold voltages to individual pins within the same IOB restricts the optimization of threshold voltages for each detector in multi-channel implementations. Lastly, the impracticality of applying a threshold when the input signal's voltage falls below 0 mV (indicating negative polarity) confines this approach to signals with positive polarity.

To overcome these shortcomings, we applied an input offset voltage (VIOFFSET) using a simple resistor and capacitor at the input receiver (Fig. 1c). This technique offers the advantage of allowing for disparate offsets for each sensor or amplifier, facilitating the identification of the optimal threshold voltage. By setting an appropriate VIOFFSET, the INTERNAL_VREF can be used in the proposed method. Moreover, when the VIOFFSET is sufficiently high, it becomes applicable to waveforms exhibiting both positive and negative polarity.

In the original SeMI approach, the external reference voltage serves as the threshold voltage (VTH = VREF). However, in the proposed method, the threshold voltage is determined by the difference between the reference voltage and input offset voltage (VTH = VREF—VIOFFSET).

In addition to apply the offset voltage at the input terminal, we propose a method to apply different VREF in a same IOB. In the SeMI method, employing two distinct threshold voltages necessitates the use of two separate IOBs with different reference voltages. This setup complicates the PCB design because the same signals must be branched to different IOBs at relatively distant locations (Fig. 2a).

Illustration of routing complexity for a existing SeMI method, and b proposed method

The proposed approach, called single-ended heterogeneous interface (SeHI), combines different types of single-ended IO standards to set different threshold voltages on the IO pins in the same IOB. Specifically, we applied SSTL/HSTL to one IO pin, while adopting other defined IO standards such LVCMOS or PCI33 for another IO pin. When utilizing digital input receivers such as LVCMOS or PCI33, a fixed reference voltage is applied internally within the FPGA, which is different from the reference voltage used by SSTL/HSTL. As a result, this configuration allows two adjacent IO pins in the same bank to have different threshold voltages (Fig. 2b, for example, SSTL/HSTL on one and PCI33 on the other). This method effectively reduces routing complexity by enabling the connection of the same signal lines to adjacent IO pins. Consequently, it lowers the number of layers needed for PCB construction, leading to reduced manufacturing costs. This approach is especially advantageous for mitigating crosstalk and minimizing induced electrical noise among signal paths.

We verified the feasibility of the proposed method using XILINX's Artix-7 FPGA (XC7A75T-1CSG324C). The supply voltage (VCCO) of the IOB used was set to 2.5 V. Unlike SSTL/HSTL IO standards where the reference voltage is set to an exact internal or external voltage, the reference voltage in LVCMOS or PCI33 is VCCO dependent and is not explicitly defined by the manufacturer. Therefore, we determined the reference voltage of LVCMOS and PCI33 under the set conditions (VCCO = 2.5 V) through the experiments.

The reference voltage serves as the threshold that digitally distinguishes between logic high (1) and logic low (0) signals. By supplying the same voltage as the reference voltage to the IO pin, we ensure that the FPGA recognizes both states, 1 and 0, equally. Leveraging this principle, we conducted an experiment where we varied the voltage input to the IO pin from 1 to 1.3 V in increments of 0.01 V. At each voltage level, we measured the ratio at which the FPGA recognized the input of the IO pin as logic high. We also conducted a reverse process, adjusting the voltage from 1.3 V back to 1 V, to observe any hysteresis effects. The reference voltage was identified at the point where ratio recognized as logic high reached 0.5.

We developed a cost-effective multi-channel DAQ board (BASP-10011; Brightonix Imaging Inc., South Korea) by applying proposed technology to demonstrate the concept of an FPGA-only digitizer in PET application (Fig. 3). This board is designed to process 16 energy channels (Ch0E—Ch15E) and 16 timing channels (Ch0T—Ch15T). The signal fed into the energy channel undergoes sampling by an 80 MHz free-running ADC, which is subsequently subjected to baseline correction and integration processes to yield precise energy information.

FPGA-based digitizer implemented for proof of concept. a Schematic and b photograph

For timing channels, an RC circuit was used to set the input offset voltage (VIOFFSET). Each timing channel input is connected to a pair of adjacent IO pins within the same IOB. These IO pins are configured to comply with SSTL and PCI33 IO standards, respectively. The low and high thresholds are adjustable based on the external reference voltage for SSTL (VREF,SSTL, supplied by the VREF pin), reference voltage applied to the PCI33 IO standard (VREF,PCI33, determined experimentally via logic high ratio test) and VIOFFSET, setting the threshold according to the following equation.

The VIOFFSET and VREF,SSTL were precisely controlled by the 16-bit digital-to-analog converter.

The incoming signal to the timing channel is converted into a digital signal by the input receivers with different threshold voltage, then transferred to the time-to-digital converter (TDC). To achieve accurate time information, the FPGA-based TDC was developed using a tapped delay line (TDL). The TDL was implemented using CARRY4 logic, resulting in a total of 180 taps formed by 45 CARRY4 logic elements (Fig. 4). Both sum (O) and carry-out (CO) output of the CARRY4 is captured through a flip-flop to improve differential nonlinearity (DNL) and integral nonlinearity (INL) performance [16]. Subsequently, the output thermometer code from flip-flop is transformed into binary code by a thermometer-to-binary converter with an integrated bit error correction function, generating a fine code value. The fine code and coarse count, produced by a counter operating at 400 MHz, are converted to timestamp, with a least significant bit (LSB) of 16 ps, through calibration logic.

Schematic drawing of TDL-based TDC

The collected time and energy information is organized into packets using a first-in, first-out (FIFO) buffer. Following data processing, these packets can then be transmitted to a workstation using the USB 3.0 protocol or to a signal multiplexing board for channel expansion through a customized LVDS protocol.

The logic design, implemented on the XC7A75T-1CSG324C FPGA, utilized the following resources: 40,754 Flip-Flops (FFs), or 43.17% of the total FFs available; 31,435 Look-Up Tables (LUTs), representing 66.6% of the FPGA's LUT capacity; and 135 pins, accounting for 64.29% of the total pins.

To evaluate the intrinsic performance of the implemented FPGA based TDC, identical temporally random digital pulses with rise time 1 ns and pulse height 0.5 V were applied to all 16 timing channels. The intrinsic timing uncertainty of the TDC was measured by obtaining the time resolution for different TDC pairs.

Figure 5a shows an experimental setup to assess the feasibility of a cost-effective FPGA-only digitizer for TOF PET applications using proposed method. Two identical one-to-one coupled detectors were assembled for coincidence data acquisition. These detectors featured polished LYSO (Lu1.9Y0.1SiO4:Ce; EPIC crystal, China) crystals with 3 × 3 × 20 mm3 dimension. The crystals were enveloped enhanced specular reflectors (ESR; 3 M, USA) on five sides, leaving one surface as the light exit surface. The crystals were optically coupled to single-channel SiPMs with an active area of 3.72 × 3.72 mm2 and 30 × 30 μm2 microcells (AFBR-S4N44C013; Broadcom, USA), featuring a total of 15,060 microcells and a fill factor of 76%. The bias voltage for the SiPMs was set at 36 V.

a Experimental setup for PET detector performance evaluation. b Configuration of amplifier circuit to optimize detector performance

To optimize timing performance, high-frequency timing signals were generated using a balun amplifier and a high-frequency amplifier [28,29,30], and the low frequency energy signals were derived from the anodes (Fig. 5b). The energy signal was split into two branches: one fed into the energy channel (ChxE), and the other directed to the timing channel (ChxT) of the BASP-10011 board. This configuration allows for the simultaneous acquisition of energy information through ADC and dual-threshold TOT. The energy value obtained by ADC is used as a reference only to evaluate the performance of dual-threshold TOT. The timing signals were directed into the other timing channels to capture the timestamp from the low threshold, while the high threshold functioned as a validation signal to minimize dead time.

Coincidence data were collected using a 22Na point source under controlled conditions, with the SiPM biased at 36 V and the experiment conducted at a stable temperature of 25 °C. For the dual-threshold TOT implementation (timing channel with energy signal), the low threshold was set at 50 mV, while the high threshold was set to 200 mV. Energy information from dual-threshold TOT was extracted using two methods. The first method involved direct estimation from pulse width, specifically the rise edge from the low threshold and the falling edge from the high threshold. The second method utilized curve fitting the scintillation pulse through bi-exponential modeling of four data points obtained through dual-threshold TOT. Subsequently, the energy information obtained through dual-threshold TOT was compared with the precisely measured energy values obtained together using an ADC. To evaluate linearity of dual-threshold TOT method, the estimated energy from TOT was compared with the energy obtained using an ADC. As an indicator of the linearity, INL was calculated as follows [22].

$$INL_}}} (E) = \frac}) - h(100})}}$$

(3)

$$INL_ = \max [INL_}}} (E)]$$

(4)

$$INL_ = \min [INL_}}} (E)]$$

(5)

$$INL_ = \frac } \right| + \left| } \right|}}$$

(6)

where energy transfer curve h(E) is the energy acquired by using the dual-threshold TOT as a function of energy acquired with ADC, f(E) is the best-fitted straight line to h(E). From the acquired data, h(E) was calculated at a 20 keV interval.

For timestamp pick-off (timing channel with timing signal), the high threshold remained constant at 200 mV, while the low threshold varied from 10 to 200 mV in increments of 10 mV to investigate the impact of varying threshold settings on time resolution performance.